Mass measurement system for mass spectrometers

ABSTRACT

In a scanning mass spectrometer, electrical output signals including a series of time-related peaks representing an ion mass spectrum of an unknown sample material are produced along with a series of reference peaks derived from a reference material. The time at which a spectrum peak occurs is taken to be the time of occurrence of the centroid (or center of gravity) of the peak. The time of occurrence of the peak centroid in relation to the time of occurrence of the end of the peak is determined and that information is presented in digital form. The occurrence time of the peak centroid is then subtracted from the occurrence time of the peak to provide the peak centroid occurrence on the scan. Thus, the time positions of the peak centroids due to an unknown sample may be readily identified with respect to the time positions of the centroids of peaks due to the reference material.

United States. Patent Banner et a].

[54] MASS MEASUREMENT SYSTEM FOR MASS SPECTROMETERS Inventors: Aubrey E.Banner, Sale; Thomas 0.

Merren, Hale, both of England Industries [73] Associated ElectricalLimited, London, England Filed: Apr. 14, 1970 App]. No.: 28,468

Assignee:

[30] Foreign Application Priority Data References Cited UNITED STATESPATENTS 8/1961 lsley, Jr. ..328/111 X 10/1961 Wilson ..324/181 [1965Keyes ..328/111 X 4/1967 Blake ..328/111 X 10/1967 Van der Lans..328/110 X 1 Mar. 27, 1973 3,363,187 [/1968 Hickin ..324/18l X3,370,228 2/1968 Mills ..328/109 3,521,046 7 1970 Le Vell Tippetts........23s |s3 x 3,541,318 11/1970 Miller ..,...235/183 Primary Examiner-Felix D. Gruber Attorney-Watts, Hoffmann, Fisher & Heinke In a scanningmass spectrometer, electrical output signals including a series oftime-related peaks representing an ion mass spectrum of an unknownsample material are produced along with a series of reference peaksderived from a reference material. The time at which a spectrum peakoccurs is taken to be the time of occurrence of the centroid (or centerof gravity) of the peak. The time of occurrence of the peak centroid inrelation to the time of occurrence of the end of the peak is determinedand that information is presented in digital form. The occurrence timeof the peak centroid is then subtracted from the occurrence time of thepeak to provide the peak centroid occurrence on the scan. Thus, the timepositions of the peak centroids due to an unknown sample may be readilyidentified with respect to the time positions ABSTRACT of the centroidsof peaks due to the reference materi- 36 Claims, 9 Drawing Figures 2DOUBLE- wzlrs PRINT 4 Mes/24;] OM05? CQNTROL caweot 44 i J i ?0 205 t 2a5% IDEA/T we 1': 56 CONTROL SUBTEA 22 a4 4 46 45, cars. come are/easeBUFFER EEG/fll. Pz/vr DENT-OUT cLocz REGISTER I 9702! sneer 641E umr IL50 L42 I L/ I I I vlslcau/vrse com o-r52 PEWTEE I 52, Tesr /55 L j7nse747= DISPLAY L PUNCH PATEMEUHARNIQB 3,723,713

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PRIOR ART INVENTOR5 AUBREY E. BAA/NEE THOMAS O, MEg

A TTOENE Y5 BACKGROUND THE INVENTION 1. Field of the Invention Thisinvention relates to mass spectrometers, and, more particularly, to amass measurement system for a scanning mass spectrometer in which anunknown sample maybe identified by the time position of its peakcentroid with respect to the time position of the peak centroids of areference material.

1. Description of the Prior-Art Mass spectrometry is a known method oftesting material to ascertain its compositiomln a mass spectrometer, amaterial being analyzed is first ionized. In one class of massspectrometers, the ions. are accelerated and then passed through anelectrostatic field to a monitor collector. The ions to be analyzed passthrough the monitor collector and then through a mag? netic field. Afterthe ions pass through the magnetic field, they are received by acollecting device. The coaction of the acceleration, the electrostaticfield, and the monitor collector separates undesired ions from thosewhich are to be analyzed. Analysis of the information gathered by thecollecting device can identify the quality or nature of the ions whichreach the collecting device. ,7 I

The physical principle upon which mass spectrometers operate is thateach ion has a characteristic mass/charge ratio. As the ion passesthrough the electrostatic and magnetic fields, it is deflected by theelectrostatic charge and then amount of deflection is a function. of themass of the ion, the speed at which the ion is traveling, and thestrength of its electric charge. By varying the strength of theelectrostatic field or the magnetic field, ions having variousmass/charge ratios are caused to impinge on the collecting device. Thisaction of varying the strength of the electrostatic field or themagnetic field is known as scanning.

It is known to introduce a reference compound having a known mass/chargeratio into the mass spectrometer along with the unknown material to bedetermined. As the spectrometer scans, its electrical output from thecollecting device will include a series of timerelated peaksrepresenting an ion mass spectrum of the unknown sample of materialalong with a series of reference peaks derived from the referencematerial. Thus, the positions of the peaks with respect to time due tothe unknown sample may be identified.

of occurrence of the time/amplitude centroid of a pulse of similarwaveform, wherein the time at which a spectrum peak occurs is taken tobe the time of the centroid (or center of gravity) of the peak. Themethod and apparatus are readily used as an intermediate low costapproach to the requirements of mass measurement, overcoming thedisadvantages of the very simple systems while maintaining the accuracyobtainable with full computer systems.

. SUMMARY or THE INVENTION 1 T- [H (T)}1[G( T)], where G(T) is the valueofthc by the magnetism. The;

The mass measurement may be made in several ways, one known method beingthat of peak matching, in which the unknown peak of interest and asuitable reference peak are alternately displayed on an oscilloscope.The accurate masses of the unknown peaks are then calculated from theaccuratelyjknown masses of the reference peaks, anda knowledge of theway in which the rate of scan changes, which is itself deduced from thetimes of occurrence of the reference peaks.

Scanning methods may be very simple, such as those utilizing a paperchart, whereby the relative times at Y time at which integrating wasmade to cease due to the which the peaks occur are measured on the chartin relation to a specially provided timer trace from an accurate clockcircuit. On the other hand, they can be very sophisticated and costiy,involving a digital computer and a special interface connected directlyon-line with the mass spectrometer.

A general object of the present invention is to provide a method andapparatus for determining the time integral with respect to time of F(t)at t= T. and H(T) is the value of the integral with respect to time ofG( t) at 1* T.-

Accordingly, a method of determining the occurrence time of thetime/amplitude centroid of a pulse signal or other waveform, such as theoutput waveform of a mass spectrometerhaving a non-zero amplitude or anamplitude above a predetermined value for a period of time, comprisesthe steps of integrating the pulse signal while its amplitude exceeds athreshold amplitude toprovide a first integral signal. The firstintegral signal is then integrated during thetime that the pulse signalamplitude exceeds the threshold amplitude to provide a second integralsignal. After the amplitude of the pulse signal falls belowthethresholdjamplitude, the final value of the second integral signal isdivided by the finalv value of the first integral signal to provide asignal representative of a period'of time. That signal is thensubtracted from the time at which integrating was made to cease due tothe amplitude of the pulse signal falling below the threshold amplitude,thus determining the occurrence time of the time/amplitude centroid ofthe pulse signal or other waveform.

Apparatus for practicing the method of the invention to determine theoccurrence time of the time/amplitude centroid of a pulse or similarwaveform having a non-zero amplitude or an amplitude above apredetermined value for a period of time comprises first integratormeans to integrate the pulse orother waveform, while its amplitudeexceeds a threshold amplitude to provide a first integral. Secondintegrator means are provided to integrate the firstintegral, while theamplitude of the pulse or other waveform exceeds the thresholdamplitude, to provide a a second integral. Dividing means are madeoperable, when integrating is made to cease due to the amplitude of thepulse or other waveform falling below the amplitude threshold, to dividethe final value of the second integral by the final value of the firstintegral to provide a signal representative of the period of time.Subtracting means then operate to subtract that period of time from theamplitude of the pulse or other waveform falling below the thresholdamplitude, thus providing the time of occurrence of the time/amplitudecentroid of the pulse or other waveformunderinvestigation.

Preferabiy the apparatus also "includes means to record and/or displayan occurrence time; Storage nieans rnay be provided betweenthesubtracting means and the recordldisplay'means, so that where peaksoccur so frequently that one occurrence time cannot be recorded ordisplayed before the next has been obtained, occurrence times are notlost or made inaccurate by relatively slow speed of operation of therecord/display means compared with the speed of operation of theintegrating, dividing and subtraction means.

More than one pair of integrating means may be provided, each pairhaving a different sensitivity, thereby increasing the dynamic range ofthe apparatus. The outputs will normally be taken from the mostsensitive pair of integrating means, but, should it saturate, the nextmost sensitive pair of integrating means will be employed, and so onthrough the pairs available. Every pair of integrating means isintegrating simultaneously. Selection means are preferably providedautomatically to change to the outputs of another less sensitive pairupon saturation of the first pair.

The invention is particularly applicable to a scanning mass spectrometerin which, although it does not directly provide the elementalcompositions of a mass spectrum, the invention nevertheless provides arelatively inexpensive method of obtaining all of the necessaryinformation for determination of accurate masses and hence of elementalcompositions.

BRIEF DESCFIFIIONO'F THE liltZWlNGS FIG. 1 is a diagrammatic sectionalelevation of one type of mass spectrometer to which the invention' maybe applied;

FIG. 2 is a block diagram illustrating the measurement system of theinvention;

FIGS. 3a and 3b are diagrams of control circuitry shown in block form inFIG. 2;

FIG. 4 is a diagram showing two pairs of integrators and a dividerincorporated in the block diagram of FIG.

FIG. 5 is a diagram of the write circuitry of the invention;

FIG. 6 is a diagram of the print circuitry embodied in the invention;

FIG. 7 is a block diagram illustrating an arrangement of storageregisters and gates applicable to the system of the invention; and

FIG. 8 is a block diagram of another embodiment of the invention.

FIG. 1 illustrates a mass spectrometer, which includes an ion sourcechamber 1 into which a specimen carrying probe 3 can be inserted and inwhich ions can be liberated from a specimen carried by the probe. Anelectrode 5, to which an accelerating voltage is applied, serves torepel these ions as a beam which passes first through an electrostaticanalyzer 7, including opposed conductive plates 7P between which apotential difference is maintained, and then through an intermediateslit member 9 into a magnetic analyzer 11. In.

the magnetic analyzer 11, an electromagnetic coil 11C establishes astrong magnetic field directed in a direction transverse to the path ofthe ions, and, since the ions are charged particles, their path will becurved in the magnetic field. The deflected ions, or certain of them itdifferent groups of ions are deflected to different degrees, passthrough an adjustable slit in output means 13 and are picked up by acollector electrode 15 associated with an electron multiplier 17.

A mass spectrometer as thus far described is well known in the art, andthe output from the electron multiplier 17 is used, after amplification,to provide a record of the number of ions passing through the adjustableslit in the member 13. The angular deflection of an ion in passingthrough the magnetic analyzer It will depend upon the acceleratingvoltage, since that determines the speed of the ions, the intensity ofthe field in the analyzer l1, and the mass of the ion. One method ofscanning a large range ofa mass spectrum is to maintain the voltagesused in the electrostatic analyzer 7 and on the accelerating electrode 5constant, and scan by varying the current used to energize theelectromagnet coil 11C of the magnetic analyzer 11. This progressivelychanges the deflections of all the ions passing through the magneticanalyzer, so that the output from the electron multiplier 17 indicatesthe number of ions passing through the slitted member 13, and whenpresented on a cathode ray tube as the vertical deflection with ahorizontal scanning speed cor responding to the decay or growth of themagnetic field in the magnetic analyzer 11, the trace shows peaks whereions having such a mass number that they are deflected to pass throughthe slitted member 13 are present.

In order to understand the operation of the method and apparatus of theinvention, consideration of the mathematical principles involved will behelpful.

Let the input signal to the first integrator of a double integrator (twocascaded integrators) be defined as F (t) between the threshold times t0 and z T. The integrated signal is also a function of t, increasingcontinuously during the period T, while the signal remains abovethreshold. Let the value of the integral at time t be G( t), I

where G(t)=L F(t)dt.

- The also of t, and is given by H( t), where the final output G(T) ofthe first integrator; i.e., the divider circuit gives the ratio[H(T)]/[G(T)], where Q I Fmd:

lset the position of the peak centroid be given by t t Then, theequation below follows directly from the definition of the centroid withrespect to the line 2 T;

.tdu (It, and do I I" I )(ll.

7 1' V T 5.1 udv= [uvH-j vdu 0 v 0 Substituting from equation (4) intoequation (3),

Thus, equation (2) gives v L Fmdt Therefore, substituting from equationl Hence, it follows that the time on the scan of the peak in analternative form of the apparatus, separate dividing means are providedfor each channel within the double integrator 24. The connectionsbetween the integrators and the dividing means are then notdependent-upon the selection means contained in the control circuitry'22. However, a different form of selection means is then used toselect'the output signal from the appropriate dividing means accordingto which channel of the double integrator 24 is in use. in either case,the output of the dividing means 26 is in digital formand is p fsuppliedas one'input to subtracting means 2 A crystal controlled clock 30 sendsregular pulses to a counter 32 which serves to add the pulses. 'Thecounter 32 may be a conventional six-decade, binarycoded decimalcounter, which receives a pulse from the clock 30 every 2.5 microsecondsduring a'ten second;

scan of the mass spectrometer.

A threshold detector not shown) in the controlled circuitry 22 isconnected to the input lead 20, and serves to detect when the output ofthe mass spectrometer exceeds a 7 threshold value. When the thresholdvalue is exceeded, that is when the mass spectrometer output commences apeak, the threshold demotor in the control circuitry 22 is triggered bythe next clock pulse from the crystal controlled clock 30 and ac tuatesthe integrating means 24 to commence'integration of the output of themass spectrometer. As previcentroid is determined by subtracting theoutput of the divider circuit from the time on the scan of the end ofthe peak. v p

As shown in block diagram form in FIG. 2, apparatus constructed inaccordance with the invention for deter- I mining the occurrence timesof output peaks during a mass spectrometer scan comprises an input lead20 for connection to the output of a mass spectrometer such as thatshown in FIG. 1. The lead 20 is connected through a switch 208 intocontrol circuitry 22, and

thence into a double integrator 24 containing cascaded first and secondintegrating means. The double integra tor 24 may contain a plurality ofchannels of differing sensitivities. The proper channel-within thedouble integrator 24 is selected by means of selection means containedwithin the control circuitry 22 and its output is passed to dividingmeans 26. The selection means contained within the control circuitry 22operates to pass to the dividing means 26 the output of the moresensitive channel in the double integrator 24, unless that channel issaturated, in which case the output of the next less sensitive channelis passed to the dividing means, and so on. Selection of the properintegrating channel in the double integrator 24 is made by a leveldetector (not shown) in the control circuitry 22.

ously noted, a double integration is performed in the .doubleintegrating means 24, and first and second in-' tegrals of the output ofthe mass spectrometer are provided to the dividing means 26 from thedouble integrator 24.

When the output of the mass spectrometer falls below the thresholdvalue, that is, when the peak has finished, the threshold detector inthe control circuitry 22 is again triggered by the next clock pulse fromthe crystal controlled clock 30. This causes the integrating means 24 tocease integrating and also causes the divid- I ing means 26 to dividethe output of the second integrator (the second integral H(T)) by theoutput of the first integrator (the first integral G(T)). At the, sametime, when the threshold detector in the control circuitry 22 istriggered at the end of a mass spectromete'r'peak, it causes a storageregister 34 to record the count state in the counter 32, thereby torecord the-time on the scan T at which integrating ceased. It isarranged that this recording does not affect the count state in thecounter 32.

When the dividing means 26 has completed dividing the second integral bythe first integral to' provide a signal indicative of-the period of time[H(T)] /[G(T)] between the time t, of occurrence of the centroid of theoutput peak in the mass spectrometer and the time Tof cessation ofintegration (i.e., the end of the peak), the subtracting means 28subtracts the period of relative time [H(T)]/[-G(T)] obtained from thedividing means 26 from the absolute time T count stored by the storageregister 34 to give theabsolute time t at which the centroid of the peakoccurred during the mass specsive outputs of the subtracting means 28until they can be printed out.

A register selector circuit 42 controlled by a print selector circuit 44selects the registers within the buffer store 40 in the order in whichthe registers stored signals from the subtracting means 28, and passesthese signals through a print gate 46, also under control of the printcontrol circuit 44, to a print-out unit 48. The buffer store 40 iseffective to prevent loss or distortion of the signals from thesubtracting means 28, due to peaks. which occur more rapidly than can beprinted out by the print-out unit 48.

The print-out unit 48 may take one of several forms. For example, it maycomprise a number of extra galvanometers (not shown) in an ultravioletchart recorder used to record the mass spectra, the number ofgalvanometers being equal to the number of decades in the binary-codeddecimal counter 32. Each binarycoded decimal counter is scanned throughthe four bits of data in its respective decade and the data is printedout in binary-coded decimal form as a horizontally spaced series ofvertical strokes on the recorder chart paper, a long stroke, forexample, representing a logical "l," and a short stroke correspondinglyrepresenting a logical 0."

To economize on the length of paper required to receive the printed outresults, it is preferred that the data corresponding to successive peaksbe vertically displaced alternately upwards and downwards by an amountslightly greater than the height of a long stroke to vertically staggeralternate print-outs. This avoids the necessity of leaving horizontalspaces between data groups printed on the chart paper.

An alternative form of print-out unit is shown in dashed lines at 50 andis known as a Honeywell Visiprinter, which prints out data in numericalform.

Still another alternative form of print-out unit is a paper tape punchindicated generally at 52, which enables accurate time data to be fedlater to an off-line computer (not shown) which could calculate accuratemasses and hence elemental compositions.

As a further alternative, the peak centroid times t, can be takendirectly from the output of the subtracting means 28 (by way of thewrite gate 36) and fed to an on-line computer denoted generally at 54,thus bypassing the buffer store 40. The computer can calculate theaccurate masses of the substance being analyzed in the massspectrometer, the results being printed out on the Visiprinter 50 or bythe print-out unit 48. Alternatively, a very fast printer,'known as astrip printer, could be used.

Some peaks will not have their centroid times calculated due to theiramplitudes always being below the threshold value. Also, some centroidtimes may be omitted if peaks occur so frequently that the buffer store40 is temporarily completely filled. Therefore, to avoid confusion inthe results, it is preferred to identify on the recording of the massspectrometer output those peaks whose centroid times have beendetermined. The identification may be made by an additional trace on therecord of the results obtained, and may take the form of a shortvertical stroke adjacent and aligned with the peak whose centroid timehas been determined. In this case, the absence of a stroke adjacent apeak will indicate that the peak was either below threshold or that thebuffer store 40 was, at the relevant time, completely filled and henceunable to accept a further centroid time. A peak identifier galvanometer56 is provided for this purpose and is driven by an output signal fromthe write control circuitry 38. The derivation of that output signalwill be described in detail in connection with the circuit diagram ofthe write control circuitry.

A simple means for calibrating the apparatus is provided by connecting asignal from the crystal controlled clock 30 through the switch 208 tothe input of the control circuitry 22. With the apparatus operational, asynthetic peak constituted by a square pulse of 0.5 millisecond durationderived from the crystal controlled clock 30 is utilized. The centroidof a square pulse lies at the center of the pulse, and therefore thetime [H(T)]/[G(T)] between the calculated centroid time (t,,) of asynthetic peak and the end of the peak (T) should be 0.25 milliseconds.This may be ascertained by connecting a suitable test display 58 to theoutput of the dividing means 26. lf'the clock 30 is delivering a pulseevery 2.5 microseconds to the counter 32, the test display 58 shouldindicate a count of one hundred. A different figure will indicate thatthe apparatus is incorrectly calibrated, and appropriate adjustments maybe made to suitable trimming potentiometers (not shown in FIG. 1) in thedouble integrator 24 and in the dividing means 26. For optimumperformance, synthetic peaks of various widths and heights are used, andadditional adjustments are made to the trimming potentiometers in thedouble integrator 24 and the dividing means 26.

A positive-going output signal is provided from the electron multiplier17 of the mass spectrometer through a portion of the control circuitry22 to the double integrator 24. That portion of the control circuitry 22through which the input signal is passed is shown in the upper portionof FIG. 3a and comprises a pair of operational amplifiers 60, 62. Theoperational amplifier 60 is provided with the usual feedback resistor60R and is arranged to operate at unity gain. The amplifier 60 alsoincludes a trimmer potentiometer 60T. The amplifier 62 has a similarfeedback resistor 62R and is arranged to operate at a gain of 100. Theamplifiers 60, 62 respectively drive two channels of the doubleintegrator, and thus obtain a dynamic range 100 times greater than couldbe obtained with only one channel. Output signals from the amplifiers60, 62 are negativegoing and are respectively provided on output leads64,

a 66 to the double integrator 24.

The amplifiers 60, 62 are conventional in design and are obtainablecommercially. For example, the amplifier 60 may consist of a Type SQlOamanufactured by and available from Philbrick/Nexus Research, Dedham,Massachusetts. The amplifier 62 may be a Model 211 amplifier availablefrom Analog Devices, Inc., Cambridge, Massachusetts.

The output from the more sensitive amplifier 62 is also provided on alead 68 to a level detector, shown generally by the numeral 70. Thelevel detector 70 comprises a comparison amplifier 72 having two inputs,one of which is connected to the lead 68 and the other of which isconnected to the movable arm of a potentiometer 74 that serves as athreshold control. One end of the potentiometer 74 is connected to asource of negative voltage V (not shown), and the other end is grounded.

The comparison amplifier 72 serves to compare the level of the, incomingsignal appearing on'the lead 68 with the threshold level set by thepotentiometer 74.

plifier 72 providesa positive-going output signal on a plifier 72 isalso provided to a NAND gate78 connected as'an inverter to provide anegative going output signal on a lead 80.

The comparison amplifier 72 is conventional in lead 76. Thepositive-going output signal from the am- 7 design and readily availablecommercially. For example, a suitable amplifier is known as the TypeSN727ION and is available from Texas Instruments, Incorporated, DalIas,Te'xas. i

The signals on the leads 76, 80 are provided as two inputs to a digitalthreshold flip-flop 82 shownin FIG. 3b. Although 'the invention is notlimited to its'use, the flip-flop 82 may be a Type SN747ON, which is amember of the SN74N series of transistor-transistor logic devicessupplied by Texas Instruments. This line of devices is described in apublication entitled Semiconductor and Components Data, Book 2obtainable from Texas Instruments. In order to provide a readyidentification, the nomenclature of the various input and output leadsshown in the figures of the present specification is that assigned byTexas Instruments to the SN74N series ofdevices.

When a positive signal appears on the lead 76 and a negative signalappears on the lead 80,'indicating that the level detector has beentriggered, it sets up a logical l on the J, input and a logical definedas a zero potential signal. The bistable flip-flop 82 is continuallyclocked by clock pulses from the crystal controlled clock 30 (FIG. 2),so that on the first positive clock pulse after the level detector hasoperated, the flip-flop 82 switches to a logical 1 output on its directoutput Q and a logical 0 on its inon the K, input of the flip-flop 82'.Throughout the specification, a logical is defined as a positive signaland a logical 0" is K: to provide a 7 'transistor is connected to due tostatistical noise at the leading edge of the spec- I trurn peak beinganalyzed.

The 0 output of the flip-flop 82 is also provided through a monostableflip-flop 88 to one input of a NAND gate 90 forming part of anothermonostable circuit, designated generally by the numeral 92; Themonostable circuit 92 also includes a second NAND gate 94, one of whoseinputs is connected to the output of the NAND gate 90 through acapacitor 96 and is also connected to ground through a resistor 98. Theoutput of the NAND gate 94: is fed back directly to a second inputof'the NAND gate 90; A second input of the NAND gate 94 receives asignal on a lead 100 from the dividing means 26 (FIG. 2), which willlater be described in detail. The output ofthe NAND gate 94 is providedon a lead 102 to one input of a two-input NAND gate 104, the other inputof which receives the logical 0" signal from the 6 output of theflip-flop 82. Under these conditions, the output of the NAND gate I0 104goes positive, and, since that to the ba se of a PNP transistor 106through a resistor 108, the base ofthe transistor 106 goes'positive.

The emitter of the transistor 106 (not shown) and groundJThe collectorof the transistor 106 is connected through resistors 114, 116 to thesource of negative voltage V. Thus, when the base of the transistor 106goes positive, conduction is cut off and the collector of the transistorgoes to 'V. This signal is provided on a lead 118, which is connected toa juncture of the resistors 114, 116, to the double integrator 24 (FIG.1 Y i The output of the NAND gate 94 in the monostable flip-flop 92isalso connected through a NAND gate 120 connected as an inverter andthrough a resistor 122 connected in series therewith to the base ofa PNPtransistor 124. I

The emitter of the transistor 124 is connected to a juncture of tworesistors 126, 128 connected in series between +V and g'roundhThecollector of the transistor 124 is similarly connected to a juncture oftworesistors 130, 132 connected in series between V and the collector.The juncture of the resistors 130, 132 is-connected through a lead 134to the double integrator 24 (FIG. 1). When the Q output of the flip-flop82 assumes a logic 1' condition, the transistor 124 c'onducts andprovides a positive signal on the lead 134. r

The output of the inverter 120 is also connected through a resistor 136to the base of an NPN transistor 138. The emitter of the transistor 138is connected to a juncture of two resistors 140, l42 connect'ed inseries transistors is connected through a resistor 146 to the base of aPNP transistor 148. The emitter of the transistor 148 is connected to ajuncture of two resistors 150, 152 connected in series between +V andground, and the collector of that ground through a resistor 154. Thecollector of the transistor 148 is also connected through a lead 156 tothe'dividing means 26 (FIG. 2). V

When the transistor 106 becomes non-conductive as previously described,the transistor 124 simultaneously becomes conductive. This means thatthe signal on the lead 134 goes positive. The signal on the lead 156from the transistor 148 is essentially at ground potential. This isbecause the output of the inverter 120 causes the transistor 138 to benon-conductive, which, in turn, causes its collector potential to riseand the transistor 148 to become non-conductive. It is also noted thatthe output of the inverter'120 is provided as input to delay circuitrycomprising in series connection a monostable flop 174, whose input isconnected to the'O output of the bistable flip-flop82, and whose outputis connected as input to a two microsecond monostable flip-flop outputis connected is connectedto the. juncture of two resistors 110, 112comprising a voltage divider connected between a source of directpotential 175. The output of the flip-flop 175, which consists ofanegative-going pulse, is provided on a lead 176 to the storage register34 (FIG. 2).

Signals are also provided from the control circuitry to a dividercounter 173, which is actually a part of the dividing means 26 shown inFIG. 2. A set input signal to the divider counter 173 is derived fromthe 6 output of the bistable flip-flop 82 through a two-input NAND gate177 and a second two-input NAND gate 178. One input of the NAND gate 177is connected to the 6 output of the flip-flop 82, and the second inputof that NAND gate is connected to receive clock pulses. The output ofthe NAND gate 177 is connected as one input to the NAND gate 178, theother input of which is taken from the output of the NAND gate 104.

A reset input of the divider counter 173 is provided with an appropriatesignal from the output of a 10 microsecond monostable flip-flop 180,which is triggered by a monostable flip-flop 182. The input to theflip-flop 182 is from the 6 output of the threshold flipfiop 82. Theoutput of the divider counter 173 appears on a lead 184 and is providedas an input to the subtracting means 28 and the test display 58 shown inFIG. 2.

As previously mentioned, signals on the leads 134, 118 from the controlcircuitry 22 control various functions of the double integrator 24. Thedouble integrator 24 is shown in the top portion 'of FIG. 4. The doubleintegrator 24 is shown as comprising two channels denoted A" and B" inthe drawing. Inasmuch as the two channels A, B are identical inconstruction, only one channel will be described. The same referencenumerals have been applied to corresponding parts in the two channels,those in channel A" being followed by the suffix A" and those in thechannel B being followed by the suffix B.

Each of the channels A, B, comprises three operational amplifiers 190,192, 194. The amplifiers 190, 192, 194 may be of the Type SQlOapreviously mentioned as manufactured by Philbrick/Nexus Research.

The amplifier 190 is provided with a trimmer potentiometer 196 foradjusting its zero, and with an in-- tegrating capacitor 198, the latterof which is connected between an inverting input of the amplifier andthe output of the amplifier. A non-inverting input of the amplifier 190is grounded through a resistor 200. The integrating capacitor 198 isshunted by a field effect transistor 202, whose gate electrode isconnected to the lead 118 from the control circuitry shown in FIG. 3b.

The output of the amplifier 190 is connected through a lead 204 into thedividing means 26 to be later described, and through a resistor 206 anda field effect transistor 208 to an inverting input of the amplifier192. A non-inverting input of the amplifier 192 is connected to groundthrough a resistor 210. The amplifier 192 is also provided with afeedback resistor 212 and with a trimmer potentiometer 214. The gateelectrode of the transistor 208 is connected to the lead 134 from thetransistor 124 in the control circuitry shown in FIG. 3b.

The output of the amplifier 192 is connected through a resistor 216 toan inverting input of the amplifier 194. A non-inverting input of theamplifier 194 is grounded through a resistor 218. The amplifier 194 isalso provided with a trimmer potentiometer 220. The output of theamplifier 194 is connected to its inverting input through an integratingcapacitor 222 connected in parallel with a field effect transistor 224.The gate electrode of the field effect transistor 224 is connected tothe lead 118 from the transistor 106 in the control circuitry shown inFIG. 3b. The output of the amplifier 194 is also connected through alead 226 into the dividing means 26 shown in the lower portion of FIG.4.

In each of the channels A and B of the double integrator 24, theamplifier 190 serves to perform a first integration and the amplifier194 serves to perform a second integration. Channel A integrates aninput signal applied thereto on the lead 64 from the amplifier 60 in thecontrol circuitry 22. The signal is applied through a resistor 228 tothe inverting input of the amplifier 190A. Similarly, the amplifier 190Breceives a signal from the amplifier 62 in the control circuitry, whichsignal is applied through a resistor 2283 to the inverting input of theamplifier 1908. Whether or not integrations are being performed inchannels A and B depends on the conductive states of the field effecttransistors 202, 208, 224, which states are determined by signals fromthe control circuitry 22 shown in FIG. 3b.

It is particularly pointed out that the integrating capacitors 198, 222and the feedback resistor 212 are shown merely as being representativeof a plurality of such components. For example, a plurality ofcapacitors may be connectable in parallel with the integrating capacitor198, a like plurality of resistors connectable in parallel with theresistor 212, and a like plurality of integrating capacitors connectablein parallel with capacitor 222. Selector switch means may be provided toselect the desired integrating capacitors and feedback resistor toprovide various integrating time constants for spectrometer scans ofvarious speeds.

As previously pointed out in connection with the description of FIG. 3b,when a peak from the mass spectrometer exceeds the value determined bythe threshold control, it triggers the level detector 70. This causesthe digital threshold flip-flop 82 to assume a logical l on its Q outputand a logical 0" on its Q output. This, in turn, causes a negativesignal to appear on the lead 118 to the double integrator 24 and apositive signal to appear on the lead 134 to the integrator. A negativesignal on the lead 118 causes the field effect transistors 202, 204 tobe non-conductive, thus permitting the capacitors 198, 222 to cooperatewith their respective amplifiers to perform a positive-goingintegration. The positive signal appearing on the lead 134 holds thetransistor 208 in a conductive condition, so that the output of theamplifier 192 increases negatively as that integration in the amplifier190 proceeds. Consequently, a positive-going integration also occurs inthe integrating circuit formed by the amplifier 194 and the capacitor222 to provide a positive-going signal on the lead 226. The integrationproceeds in both channels A and B until the output of the comparisonamplifier 72 in the level detector reverts to a logical 0 on its output,which occurs when the spectrum peak being analyzed falls below thethreshold.

When the Q output of the flip-flop 82 goes to logical 0, it triggers themonostable flip-flop 92, which produces an output pulse having aduration of approximately microseconds. This causes the transistor 124to become non-conductive'and provide a negative signal on the lead 134.That negative signal causes the field effect transistor 208 in theintegrator 24 to become non-conductive and further integration in theamplifier 194 is prevented.

The 150 microsecond pulse from the flip-flop 92 is also applied throughthe gate 104 to the transistor 106. At that time, the gate 104 isreceiving a logical signal from the flip-flop 92 and a logical 1 signalfrom the 6 output of the flip-flop 82. Therefore, the output of the gate104 remains at logical l," thus maintaining the transistor 106 in anon-conductive state and the transistors 202, 224 in the integrator 24in a non-conductive state. It is during this time that the divisionprocess occurs in the dividing means 26.

The channel selector, which is part of the control circuitry 22,provides signals to the dividing means 26 that determine which of theoutput signals from the channels A or B in the double integrator 24 areto be acted upon by the dividing means. The channel selector isdesignated generally by the numeral 230 and is shown in the center partof FIG. 3a. 7

The channel selector 230 comprises an operational amplifier 232 and apair of PNP transistors 234, 236. The amplifier 232 may conveniently bethe Type SQlOA previously mentioned, and is connected as a On the otherhand, when the output of the integrating amplifier [90B exceeds +10volts, the output of-the level detector amplifier 232 goes to a logical0."QThis causes the transistor 234 to become conductive'and provide anapproximately zero voltage signal on the output lead 264. At the sarrietime, the transistor 236 becomes non-conductive, and provides a negativevoltage signal on the output lead 274.

7 The dividing means 26 which provides for dividing the secondintegrated output of the double integrator 24 by the first integratedoutput isshown in the lower level detector. To this end, a non-invertinginput of the amplifier 232 is connected to ground through a resistor 238and an inverting input is connected to V through V a resistor 240. Theoutput of the amplifier 232 is connected to the cathode of a Zener diode242, whose anode is connected to ground through a resistor 244 and tothe inverting input oF the amplifier through a pair of oppositely poleddiodes 246, 248. The output of the amplifier 232 is also connectedthrough a resistor 250 to the base of the PNP transistor 234 and throughan inverter 252 and a resistor 254 to the base of the transistor 236.The emitter of the transistor 234 is connected to a juncture between tworesistors 2 56, 258, which are connected in series between +V andground. The collector of the transistor 234 is connected to'a negativesupply source through series-connected resistors 260, 262, and ajuncture of those resistors is connected to an output lead 264. Theemitter of the transistor 236 is connected to a juncture b etweentworesistors 266, 268 connected in series between +V and 7 ground. Thecollector of the transistor 236 is connected to a negative supply sourcethrough series-connected resistors 270, 272, and a juncture of thoseresistors is connected to an output lead 274.

In operation, the level detector amplifier 232 ex-, amines the output ofthe amplifier 1908 in the channel B (the more sensitive channel) in thedouble integrator 24, which output is connected 'to'the inverting inputof the amplifier 232 through a resistor 275. It will be recalled thatthe output of the amplifier 1908 is a positive-going signal when anintegration is being performed. If the output of the amplifier 190B isnot greater than, for example, +10 volts, the output of the amplifier232 in the channel selector is at a logical l This causes the transistor234 to be non-conductive, and the transistor236 to be conductive. Thus,a negative voltage signal appears on the lead 264, and an approximatelyzero voltage signal appears on the lead 274..

' portion of FIG. 4. It comprises an integrating amplifier and a fieldeffect transistor 290. Which of the field efi feet transistors 286, 290is conductive to provide a signal to 'the input of the integratingamplifier 276 depends on the signal respectively applied to the gateelectrode of those transistors on the leads 264, 274. If a the signal onthe lead 2048 is not greater than +10 7 volts, the transistor 290 willbe conductive to provide the signalfrom channel B of the integrator 24to the dividing means. On the other hand, if the signal on the lead 2048is greater than 10 volts, the field effect transistor 286 will be madeconductive to apply the signal from the channel A in the integrator tothedivider. The integrating capacitor 2 78 is shunted by a field effecttransistor 292, which must-be in a non-con-.

ductive state for the integrating amplifier 276 to be operationalregardless of which signal is applied to its inverting input. Anon-inverting. input of the amplifier 276 is grounded through a resistor294.-A signal is applied to the gate electrode of the transistor 292from,

the control circuitry on the lead l56'from the transistor 148.

The output of thefintegrating amplifier 276 is sup plied through aresistor 296 toan inverting input of, the

- amplifier 280. The inverting input of the amplifier 280..

is also connected to receive a signal from the output of the integratingamplifier 194A on the lead 226A, connected through a resistor 298 and afield effect transistor 300. The gate electrode of the transistor 3:20is also connected to the lead 264 from the channel selector 230 shown inFIG. 3a.. The inverting input of the amplifier 280 is similarlyconnected to receive a signal from the integrating amplifier 194B on thelead 2263, connected through a'resistor 302 and another field effecttransistor 304. The gate electrode of the transistor 304 is alsoconnected to the lead 274:from the channel selector 230. The output ofthe inverting amplifier 280 is connected directly to anrinverting inputof the comparison amplifier 282. A non-inverting input of the amplifier282 is connected directly to ground. The output of the amplifier 282 isconnected to the lead into the control circuitry shown in FIG..

It can be shown mathematically that the dividing means 26 is capable ofdividing the final output H(T) of the second integrator by the finaloutput C(T) of the first integrator. taking a new time origin (t=) atthe end of the input peak.

First, let J(T) be the output of the amplifier 276 at time t, the inputresistance being R and the capacitance being C.

output of the threshold flip-flop 82 goes to a logical 0," themonostable circuit comprising the flip-flops 180, 182 applies a pulse ofabout microseconds duration to the reset input of the divider counter 173 to reset the counter to 0. The logical 0 on the Q output of theflip-flop 82 also inhibits the NAND gate 177 and thus prevents clockpulses from reaching the divider counter through the NAND gate 178. Atthe end of the spectrum peak, the Q ogtput of the flip-flop 82 assumes alogical 0 and the Q output assumes a logical 1." Thus, the NAND gate 177is enabled to pass clock pulses to the NAND gate 178.

During the reception of a spectrum peak, the output of the gate 94 inthe 150 microsecond delay circuit 92 is normally at logical I." Thiscauses the transistor 138 to be non-conducting, which in turn, causesthe transistor 148 to be non-conducting and the output lead 156 to be at0 volts; This causes the transistor 292 across the integrating amplifier276 to be conducting so that no integration occurs in the amplifier 276.However, at the end of the spectrum peak, the output of the comparisonamplifier 282 is at logical l which enables the gate 94. Thus, when thethreshold flip-flop 82 triggers the 150 microsecond monostable circuit92 at the end of the spectrum peak, the transistor 292 in the dividingmeans 26 becomes non-conductive and a negative-going integrationcommences in the integrating amplifier 276. The input to the amplifier276 is the final output of the integrating amplifier 190A or theamplifier 1908 according to the spectrum size peak. As the integrationproceeds in the amplifier 276, the output of the inverting amplifier 280increases from a negative value toward zero volts. When the integratedoutput of the amplifier 276 equals the output of the amplifier 194A or19413, the comparison amplifier 282 switches from a logical 1" on itsoutput to a logical 0," thus inhibiting the gate 94 whose output goes toa logical 1." However, the Q output of the threshold flip-flop 82 isalready at logical l and so the output of the gate 104 switches tological 0." This inhibits the gate 178, thus cutting off the train ofclock pulses to the divider counter 173, the count state of which isthen held until the next peak arrives. As has previously been shown, thecount state of the divider counter 173 at this point is representativeof the time of the spectrum peak centroid from the end of the peak.

When the output of the comparison amplifier 282 switches to logical 0upon completion of the division process, and the output of the gate 104consequently also goes to logical 0," the transistor 106 becomesconductive. This causes the collector of that transistor to go toapproximately zero volts, which thus makes the field effect transistors202, 224 in the double integrator 24 become conductive. This resets theintetrating amplifiers 190, 194 to zero volts on their outputs. Also,upon completion of the division process, when the out put of the gate 94goes to logical l the transistor 124 becomes conductive. This causes thesignal on the lead 134 to switch to approximately zero volts and causesthe transistor 208 to conduct in readiness for reception of the nextspectrum peak.

As previously mentioned in connection with FIG. 2, an output of thecrystal controlled clock 30 is provided to a counter 32. The output ofthe counter 32 is supplied through a storage register 34 to thesubtractor 28. The subtractor also receives a signal from the dividingmeans 26, specifically from the divider counter 173, which signal isalso provided to the test display 58. Neither the subtractor 28, thecrystal controlled clock 30 the counter 32 or the storage registers 34are shown in other than block forms, inasmuch as they are allconventional well-known components. For example, typical circuits thatmay be used for these components are shown in a book entitled, Pulse,Digital and Switching Waveforms" by Millmau & Taub (McGraw-l-lill BookCompany, 1965).

The test display 58 consist of any conventional wellknown device such asneon tubes, Nixie tubes (Burroughs Corporation).

The centroid time data of successive peaks which are presentedsuccessively at the output of the binarycoded decimal subtractor 28, arewritten in order into the buffer registers 40 under control of the writecontrol circuitry 38 and the write gate 36. The write control and gatecircuitry is shown in logical diagram form in FIG. 5.

Fundamentally, the write control 38 comprises a conventional binarycounter shown in FIG. 5 as two flip-flops 310, 312, plus associateddecoding gates. This arrangement provides four individual count states,each one corresponding to an associated storage register in the bufferstore 40. If more than four registers are used, then the binary counterwould need to be extended accordingly. For example, the use of threeflipflops in the binary counter would allow for eight registers in thebuffer store. The flip-flops 310, 312 can conventionaly be Type SN7470Ndevices supplied by Texas Instruments, as previously mentioned. Thedecodinggates comprise four four-input NAND gates 314, 316, 318, 320 ofconventional design.

The J and K input of both of the flip-flops 310, 312 are connected to+V, so that those flip-flops act strictly as counters. The Q output ofthe first flip-flop 310 is connected to one of the inputs of each of theNAND gates 316, 320, and so the 6 output that flipflop is connected toone of the inputs of the other two NAND gates, namely the gates 314,318. The 6 output of the first flip-flop 310 is also connected to theclock input of the second flip-flop 312. The Q output of the flip-flop312 is connected as one input to each of the NAND gates 318, 320, and sothe 6 output of the flip-flop 312 is connected to one of the inputs ofeach of the NAND gates 314, 316. Thus, the counter comprising theflipflops 310, 312 selects one of the four decoding gates 314, 316, 318,320 by applying a logical l to two of its inputs. The third input toeach of the gates 314-320 is provided from an associated flipflop,respectively designated 324, 326, 328, 330, each of which is associatedwith arespective storage register in the buffer store 40. The purpose ofthe flip-flops 324-330-is to provide flag signals on their Q outputs toindicate L whether or not data is already stored in the correspondingregister. The flip-flops 324-330 may also conveniently be of the SN740NType previously described.

The 6 output of each of the flip-flops 324-330 is connected to the thirdinput of its associated NAND gate 314-320 through a NAND gate and aninverter connected in series. The Qoutput of the flip-flo p 324 isconnected to one input of a NAND gate 334 whose output is connectedthrough an inverter 334i to the NAND gate 314. The output of theinverter 3341 is also connected directly to the 1 input of the flip-flop324 and through an inverter 3241 to the K input of that flipflop. Theclock input to the flip-flop 324 is provided from the output of a NANDgate 324C, one of whose inputs is a slightly delayed output of the NANDgate 314. This is caused by the output of the NAND 314 being connectedto trigger a flip-flop 314F whose output in turn triggers a onemicrosecond delay flip-flop 314D. The otherinput to the NAND gate 324Cis from the print control circuit 44. The Q output of the flipflop 324is provided to the print control circuit 44.

Inasmuch as the pattern of numbering the components in the other threechannels of the write control circuitry follows that just described withrespect to the first channel, and the componentsof the four cha hnels'is then impossible because of the inhibited input to the correspondingdecoding gate 314-32 0 to write any new data into the register until thethen present data has been printed out and the flag signal removed.

The outputs of each of the delay flip-flops 314D-320D are connected todifferent inputs of atominput NAND gate 335. The output of the NAND gate335 is connected through an inventor 3351 and thence through a flip-flop335E and a 0.5 microsecond delay flip-flop 3351) to the peak identifiergalvanometer 56 shown in FIG. 2.

Whenever one of the monostable circuits 314D-320D following the decodinggates 314-320 is triggered by a write command pulse, then the delaycircuit 335D is triggered to cause the peak identified galvanometer 56to be deflected. 1f the selected store already contains information notyet printed out, then no pulse is obtained from the correspondingdecoding gate v 314-320, and consequently the peak identifier gal- Vvanometeris not deflected. It is, therefore, clear on the record whichpeaks have been handled by the circuitry embodying the invention. Thevarious components comprising the printing circuitry are shown in logicdiagram form in FIG. 6. Basi cally, the print control circuit-comprisesa simple binary counter similar to that previously described with areidentical, the connections of the components of the circuitry 22. A Kinput to the flip-flop'332 is also provided from the lead 172 after itpasses through an inverter 3321. The signal present on the lead 172 fromthe control circuitry 22 is a rough command pulse which is derivedbasically from the returning edge of the pulse derived from thethreshold flip-flop 82 after a suitable time delay. The flip-flop 332produces a write command pulse when the flip-flop is triggered by acommand pulse applied on its C input from the crystal controlled clock.a

In operation, if there is no data already present in the selectedregister, the output of the selected decoding gate 314-320 switches to alogical O." This triggers its associated monostable circuit 3140-3201)and applies a trigger pulse to the associated flag flip-flop 324-330.Thus, the affected flag flip-flop provides a logical 1 on its directoutput O. This signal is connected into the print control circuitry, aswill be laterdescribed.

The output from each of the monostable circuits 314D-320D is connectedto a respective output lead 314S-320S, which is connected to arespective data strobe input of the storage registers, whereby the datathen present on the data inputs to the storage register is copied intothe selected register. Since the flag has been put up by the associatedflag flip-flop 324-330, it

respect to the write control circuitry 38 and embodying components ofthe same type, along with suitable decoding circuitry. The print controlbinary counter comprises a pair of flip-flops 336, 338. The J and Kinputs of both of the flip-flops 336, 338 are connected to +V, and onlythe C input received pulses. The C input of the flip-flop 336 isconnected to the output of a twoinput NAND gate 340, which continuallyreceives clock pulses. The Q output of the flip-flop 336 is connected tothe C input of flip-flop 338. Thus, the flip-- flops 336, 338 arecapable of giving four individual count statespThe clock pulses aregated into the flipflop 336 bya signal present on the second input ofthe NAND gate 340. That signal is provided through an inventer 342 fromthe outputsof various gates in the print control circuit.

The decoding circuitry comprises four NAND gates i 344, 346, 348 and350, each of which NAND gate has two inputs. The Q output of theflip-flop 336 is con-', nected to one input of each of the NAND gates346, 350, and the 6 output of that flip-flop is connected to one inputof each of the other two NAN-D gates 344, 348. The Q output oftheflip-flop 338 is connected to oneinput of each of the the NAND gates348, 350 and the Q output of the flip-flop is connected to an input ofeach of the remaining NAND gates 344, 346.

The output of each of the NAND gates 344-350 is inverted by acorresponding inverter 3441-3501, whose output is applied to one inputof a corresponding twoinput NAND gate 344G-350G. The other input of eachof the gates 344G-350G is provided from the direct or Q output of thecorresponding flag flip-flop 324-330 in the write control circuitryshown in FIG. 5. If data is present in the corresponding register,theflag is up and the Q output of the corresponding flag flip-flop 7324-330 is at logical 1. Thus, the output of the corresponding gate344G-350G switches to logical O.

The outputs of the gates 3440-3506 are respectively connected to fourinputs of a NAND gate 352. The

output of the NAND gate 352 is provided through the inverter 342previously mentioned to the second input of the NAND gate 340. Thus, ifaflag is up and one of the NAND gates 3446-3506 is at logical 0, thetrain of clock pulses to the flip-flop 336 through the NAND gate 340 iscut off and the counter remains in the state it has attained at thattime.

Whenever one of the four gates 344G-350G switches to logical on itsoutput, indicating that the corresponding storage register selected bythe counter contains data ready for printing out, the output of the NANDgate 352 switches to logical l." This sets a logical "0 on the output ofthe inverter 342. This, in turn, by way ofa lead 354 and anotherinverter 356 sets logical 1" and 0" states on J and K inputs,respectively, at a flip-flop 358. This sets a logic 1 on a Q or directoutput of a flip-flop 358. The flip-flop 358 may be of the SN747OWN Typepreviously mentioned.

The Q output of the flip-flop 358 is connected to one input of atwo-input NAND gate 360, the other input of which is connected toreceive clock pulses.

The output of the NAND gate 360 is connected as input to a print cyclecounter 362. The print cycle counter 362 governs the operation ofprinting out data from the buffer store onto recorder charge paper bymeans ofa set of galvanometers (NOT SHOWN). Such galvanometers form partof the printout unit 48 shown in block form in FIG. 2.

The counter 362 provides four outputs A,B,C,D, respectively representing2', 2, 2 and 2 which are respectively supplied to four inverters 362A,B, C & D. The outputs of the inverters 362A-D are supplied as fourinputs to a NAND gate 364. The outputs of the inverters 362A-C are alsosupplied as three inputs to a NAND gate 366, whose fourth input isprovided directly from the D output of the counter 362. The out puts ofthe NAND gates 364, 366 are provided as inputs to another NAND gate 368,whose output is inverted by an inverter 370. If galvanometers are notused in the print out, but some other method of printing out the data isused, such as the Visiprinter 50 or paper tape punch 52, a print commandsignal for those devices is obtained from the output of the inverter370.

The print cycle counter 362 counts until it reaches a count state of 8or until it reverts to zero after reaching 15. At that time, the NANDgate 364 or the NAND gate 366 goes to logic 0" at its output, thuscausing the NAND gate 368 to switch to logic I on its output and theinverter 370 to switch to logical 0 on its'output.

It is noted at this point that each of the NAND gates 344, 346, 348, 350is connected through its corresponding inverter 3441-350X to one inputof a corresponding two-input NAND gate 344H-350H. Thus, when a storageregister is selected by the counter comprising the flip-flops 336, 338,the output of one of the NAND gates 344-350 will be at logical 0 and theoutput of the corresponding inverter 3441-3501 has logical 1" on itsoutput. In this condition, the other gates will be at logical l andtheir corresponding inverters will be at logical 0." Therefore, only oneof the four gates 344H-350H will be enabled.

When the inverter 370 switches its output to logical O," as previouslydescribed, it triggers two monostable circuits. The first monostablecircuit comprises two NAND gates 372, 374, and the second monostablecircuit comprises two more NAND gates 376, 378. When the inverter 370switches its output to logical 0, it

causes the output of the gate 378 to switch temporarily to logical Thiscauses the output of an inverter 380 connected to the output of the NANDgate 378 to switch temporarily to logical l." Thus, the output of theenabled gate in the set of gates comprising gates 344H-350H switches'tological 0." This causes a corresponding gate 324C-330C in the printcontrol circuitry to switch to logical 1, thus triggering thecorresponding flag flip-flop 324-330. The conditions of the J and Kinputs of the triggered flag flip-flop are such that it is reset toprovide a logical 0" on its direct or Q output, i.e., the flag is putdown after the data in its associated storage register has been printedout. The other flag flip-flops are reset in a similar way by way oftheir corresponding gates. The data in the storage register is not resetto logical O," it is simply overwritten when new data appears. As theflag goes down, the output of the gate 352 switches to a logical 0, thusmaking the output of the gate 378 go immediately to logical 1 andoverride the effect of the monostable circuit comprising the gates 376,378.

If the register selected for the print-out happens to be thatcorresponding to count state 0" in the counter comprising flip-flops336, 338, then the output of the gate 344 is logical 0," and this isapplied to one of the inputs of the gate 334 in the write controlcircuitry. Thus, the output of the inverter 334i is logical 0," whichinhibits the gate 314. The action is similar for the other registers.Thus, while the print control counter flip-flops 336, 338 are selectinga given register, it is impossible to write new data to that registereven though the flag may have just been put down. This is a verynecessary condition in order to avoid queuejumping.

It has just been shown that as the flag of the selected flag flip-flop324-330 corresponding to a selected storage register is reset to logical0 on its Q output after printing out of data, the output of the gate 352in the print control circuitry switches to logical 0. This causes theoutput of the inverter 342 to switch to logical 1." Thus, the J and Kinputs of the flip-flops 358 are put in logical 0 and logical 1"conditions, respectively. This occurs very shortly after the print cyclecounter 362 reaches a count state of 0 or 8, because the time taken toreset the flag flip-flop 324-330 corresponding to any one of the storageregisters is only a matter of a few tenths of a nanosecond. Since theprint cycle counter 362 is clocked by positive-going edges of the clockpulses, the J and K inputs of the flip-flop 358 are set to theirappropriate levels well before the next negative-going edge from theclock which, therefore, clocks the flip-flop 358 to give a logical 0" onits direct or Q output. This output inhibits the gate 360, which thenprevents further trigger pulses from reaching the print cycle counter362. Thus, the print cycle counter remains at the count state of 0 or 8until the next register containing data is selected and the flip-flop358 is consequently set to logical l on its Q output, and the completeprinting cycle is repeated.

FIG. 7 illustrates diagrammatically the storage registers comprising thebuffer store 40 and the print gate 46. Storage registers 324R-330Rcorresponding to the flag flip-flops 324-330 in the write controlcircuitry (FIG. 5) all receive input data from the subtractor 28. Theregisters 324R-330R also receive strobe signals from the flip-flops314D-320D, respectively, on the

1. In a system for determining mass of an ion in a scanning massspectrometer by determining time of occurrence of a centroid of anoutput peak signal due to said ion with respect to time of occurrence oftermination of said peak signal, the combination comprising: a. firstintegrating means for integrating said peak signal to obtain a firstintegral signal; b. second integrating means for integrating said firstintegral signal to obtain a second integral signal; c. dividing meansfor dividing said second integral signal by said first integral signalto provide a time signal proportional to the time of occurrence of saidcentroid relative to said time of occurrence of said termination of saidpeak signal. d. threshold detecting means for obtaining a terminationsignal indicating said termination of said peak signal; and, e.subtracting means for subtracting the value of said time signal from thevalue of said termination signal to obtain a signal having a valuerepresentative of said time of occurrance of said centroid.
 2. Thecombination of claim 1, further including means for developing saidfirst and second integral signals only during the period of time thatthe amplitude of said peak signal exceeds a threshold amplitude.
 3. Thecombination of claim 2, wherein said first and second integrating meanseach comprise a like plurality of channels having differentsensitivities.
 4. The combination of claim 3, further including channelselector means responsive to amplitude of said output signal of saidmass spectrometer for applying said output peak signal to a selected oneof said channels of said first integrating means and a selected one ofsaid channels of second integrating means.
 5. The combination of claim1, wherein said first and second integrating means each comprisescomprise like plurality of channels having different sensitivities. 6.The combination of claim 5, further including channel selector meansresponsive to amplitude of said output signal of said mass spectrometerfor applying said output peak signal to a selected one of said channelsof said first integrating means and a selected one of said channels ofsecond integrating means.
 7. The combination of claim 1, wherein saiddividing means includes a counter for providing said signalrepresentative of A period of time.
 8. The combination of claim 7wherein said dividing means includes an integrator and a comparator forreceiving said first and second integral signals for providing to saidcounter a signal having a time duration representative of said secondintegral signal divided by said first integral signal.
 9. Thecombination of claim 8, wherein said integrator receives and integratessaid first integral signal to provide a third integral signal and saidcomparator receives said second and third integral signals and causestermination of said counter when said third integral signal equals saidsecond integral signal.
 10. The combination of claim 1, furtherincluding recording means for recording said signals representative ofsaid time of occurrence of said centroid.
 11. The combination of claim2, wherein said dividing means includes a counter for providing saidsignal representative of a period of time.
 12. The combination of claim11 wherein said dividing means includes an integrator and a comparatorfor receiving said first and second integral signals for providing tosaid counter a signal having a time duration representative of saidsecond integral signal divided by said first integral signal.
 13. Thecombination of claim 12, wherein said integrator receives and integratessaid first integral signal to provide a third integral signal and saidcomparator receives said second and third integral signals and causestermination of said counter when said third integral signal equals saidsecond integral signal.
 14. A system for determining occurrence time ofa time/amplitude centroid of a pulse signal having an amplitude above athreshold amplitude for a period of time comprising: a. firstintegrating means for integrating said pulse signal while its amplitudeexceeds said threshold amplitude to provide a first integral signal; b.second integrating means for integrating said first integral signalwhile said amplitude of said waveform exceeds said threshold amplitudeto provide a second integral signal; c. dividing means actuated afterthe amplitude of said pulse signal decreases to a value less than saidthreshold amplitude for dividing said second integral signal by saidfirst integral signal to provide a signal representative of a period oftime; and, d. subtracting means for subtracting said signalrepresentative of a period of time from a signal representative of thetime at which integration ceased due to amplitude of said waveformfalling below said threshold amplitude to provide an output signalrepresentative of the time of occurrence of the centroid.
 15. In asystem for determining mass of an ion in a scanning mass spectrometer bydetermining time of occurrence of a centroid of an output peak signaldue to said ion with respect to time of occurrence of termination ofsaid peak signal, the combination comprising: a. first integrating meansincluding a plurality of channels having different sensitivities forintegrating said peak signal to obtain a first integral signal; b.second integrating means including a plurality of channels havingdifferent sensitivities for integrating said first integral signal andto obtain a second integral signal; c. dividing means for dividing saidsecond integral signal by said first integral signal to provide a timesignal proportional to the time of occurrence of said centroid relativeto said time of occurrence of said termination of said peak signal. 16.The combination of claim 15, further including channel selector meansresponsive to the amplitude of said output peak signal of said massspectrometer for applying said output peak signal to a selected one ofsaid channels of said first integrating means and a selected one of saidchannels of said second integrating means.
 17. The combination of claim16, wherein said dividing means includes a counter for providing saidsignal representative of a period of time.
 18. The combination of claim17 Wherein said dividing means includes an integrator and a comparatorfor receiving said first and second integral signals for providing tosaid counter a signal having a time duration representative of saidsecond integral signal dividied by said first integral signal.
 19. Thecombination of claim 18, wherein said integrator receives and integratessaid first integral signal to provide a third integral signal and saidcomparator receives said second and third integral signals and causestermination of said counter when said third integral signal equals saidsecond integral signal.
 20. The combination of claim 15, wherein saiddividing means includes a counter for providing said signalrepresentative of a period of time.
 21. The combination of claim 20wherein said dividing means includes an integrator and a comparator forreceiving said first and second integral signals for providing to saidcounter a signal having a time duration representative of said secondintegral signal divided by said first integral signal.
 22. Thecombination of claim 21, wherein said integrator receives and integratessaid first integral signal to provide a third integral signal and saidcomparator receives said second and third integral signals and causestermination of said counter when said third integral signal equals saidsecond integral signal.
 23. In a system for determining mass of an ionin a scanning mass spectrometer by determining time of occurrence of acentroid of an output peak signal due to said ion with respect to timeof occurrence of termination of said peak signal, the combinationcomprising: a. first integrating means for integrating said peak signalto obtain a first integral signal; b. second integrating means forintegrating said first integral signal to obtain a second integralsignal; and, c. means for responsive to said first and second integralsignals for generating a signal indicative of time of occurrance of saidcentroid relative to time of occurrance of termination of said peaksignal, said means including a counter for providing said signalindicative of a period of time.
 24. The combination of claim 23 whereinsaid means responsive to said first and second integral signals includescircuit means providing to said counter a signal having a time durationrepresentative of said second integral signal divided by said firstintegral signal.
 25. The combination of claim 24, wherein said circuitmeans includes integrator means for receiving and integrating said firstintegral signal to provide a third integral signal, and comparator meansfor receiving said second and third integral signals and causingtermination of said counter when said third integral signal equals saidsecond integral signal.
 26. In a method of determining mass of an ion ina scanning mass spectrometer by determining time of occurrence of acentroid of an output peak signal due to said ion with respect to timeof occurrence of termination of said peak signal, the steps of: a.integrating said peak signal to obtain a first integral signal; b.integrating said first integral signal to obtain a second integralsignal; c. dividing said second integral signal by said first integralsignal to obtain a signal having a value which is representative of thetime of occurrence of said centroid relative to said time of occurrenceof said termination of said peak signal; and, d. obtaining a terminationsignal indicating said termination of said peak signal, and subtractingsaid time representative signal from said termination signal to obtain asignal having a value representative of the time of occurrence of saidcentroid.
 27. The method set forth in claim 26, wherein the integrationsare performed only while the amplitude of said peak signal exceeds apredetermined threshold amplitude.
 28. A method of determining the timeof occurrence of a time/amplitude centroid of a pulse signal having anamplitude above a threshold amplitude for a period Of time comprisingthe steps of: a. integrating said pulse signal while its amplitudeexceeds said threshold amplitude to provide a first integral signal; b.integrating said first integral signal while the amplitude of the pulsesignal exceeds said threshold amplitude to provide a second integral; c.dividing said second integral signal by said first integral signal afterthe amplitude of said pulse signal falls below said threshold amplitudeto provide a signal representative of a period of time; and, d.subtracting said time representative signal from a signal representativeof the time at which integration ceased due to amplitude of said pulsesignal falling below said threshold amplitude to provide an outputsignal representative of the time of occurrence of the centroid.
 29. Amethod of peak matching with a mass spectrometer comprising the stepsof: a. establishing a field with an analyzer of the mass spectrometer;b. adjusting the level of the analyzer field such that ions of a firstmass number are directed substantially toward an ion collector; c.scanning the level of the analyzer field over a range necessary to causethe waveform of a first output signal developed by the ion collectorresulting from the ions striking the collector to take the form of asignal which increases in value for a given interval of time anddecreases in value for a given interval of time to thereby define a peakamplitude; d. integrating said output signal during the scanning of theanalyzer field to provide a first integral signal; e. integrating saidfirst integral signal during the scanning of the analyzer field toprovide a second integral signal; f. dividing said second integralsignal by said first integral signal to provide a signal having a valuerepresentative of the elapsed time between the time of occurrence of acentroid of said first ion collector output signal and the terminationof the scanning; g. adjusting the level of the analyzer field such thations of a second mass number are directed substantially toward the ioncollector; h. scanning the level of the analyzer field over a rangenecessary to cause the waveform of a second output signal developed bythe ion collector resulting from the ions striking the collector to takethe form of a signal which increases in value for a given interval oftime and decreases in value for a given interval of time to therebydefine a peak amplitude; i. integrating said second output signal duringthe second scanning of the analyzer field to provide a third integralsignal; j. integrating said third integral signal during the secondscanning of the analyzer field to provide a fourth integral signal; k.dividing said fourth integral signal by said third integral signal toprovide another signal having a value representative of the elapsed timebetween the time of occurrence of a centroid of said second ioncollector output signal and the termination of the second scanning; and,l. subtracting the value of one of said elapsed time representativesignals from the value of the other elapsed time representative signalto provide a comparison signal representative of the relative positionsof the signal peaks.
 30. The method as defined in claim 29 including thesteps of: a. changing the level of the analyzer field to a differentvalue which also causes the ions of the first mass number to be directedsubstantially toward the ion collector; and, b. repeating the steps ofc) through f), and h) through l) of claim
 29. 31. The method as definedin claim 29 including the steps of a. changing the level of the analyzerfield to a different value which also causes the ions of the second massnumber to be directed substantially toward the ion collector; and, b.repeating the steps of b) through f), and h) through l) of claim
 29. 32.A method of peak matching with a mass spectrometer comprising the stepsof: a. establishing a field with an analyzer of the mass spectrometer;b. adjusting the level of the analyzer field such that ions of a firstmass number are directed substantially toward an ion collector; c.scanning the level of the analyzer field over a range necessary to causethe waveform of a first output signal developed by the ion collectorresulting from the ions striking the collector to take the form of asignal which increases in value for a given interval of time anddecreases in value for a given interval of time to thereby define a peakamplitude; d. integrating said output signal during the scanning of theanalyzer field to provide a first integral signal; e. integrating saidfirst integral signal during the scanning of the analyzer field toprovide a second integral signal; f. dividing said second integralsignal by said first integral signal to provide a signal having a valuerepresentative of the elapsed time between the time of occurrence of acentroid of said first ion collector output signal and the terminationof the scanning; g. adjusting the level of the analyzer field such thations of a second mass number are directed substantially toward the ioncollector; h. scanning the level of the analyzer field over a rangenecessary to cause the waveform of a second output signal developed bythe ion collector resulting from the ions striking the collector to takethe form of a signal which increases in value for a given interval oftime and decreases in value for a given interval of time to therebydefine a peak amplitude; i. integrating said second output signal duringthe second scanning of the analyzer field to provide a third integralsignal; j. integrating said third integral signal during the secondscanning of the analyzer field to provide a fourth integral signal; k.dividing said fourth integral signal by said third integral signal toprovide another signal having a value representative of the elapsed timebetween the time of occurrence of a centroid of said second ioncollector output signal and the termination of the second scanning; l.subtracting the value of one of said elapsed time representative signalsfrom the value of the other elapsed time representative signal toprovide a comparison signal representative of the relative positions ofthe signal peaks; m. changing the level of the analyzer field to adifferent value which also causes the ions of the first mass number tobe directed substantially toward the ion collector; and, n. repeatingthe steps of c) through f) and h) through l) until the value of thecomparison signal equals substantially zero.
 33. The method as definedin claim 32 including the steps of: a. changing the level of theanalyzer field to a different value which also causes the ions of thesecond mass number to be directed substantially toward the ioncollector; and, b. repeating the steps of b) through f) and h) throughl) of claim
 32. 34. A method of peak matching with a mass spectrometercomprising the steps of: a. establishing a magnetic field with amagnetic analyzer of the mass spectrometer; b. adjusting the level ofthe magnetic field such that ions of a first mass number are directedsubstantially toward an ion collector; c. scanning the magnetic fieldover a range necessary to cause the waveform of a first output signaldeveloped by the ion collector resulting from the ions striking thecollector to take the form of a signal which increases in value for agiven interval of time and decreases in value for a given interval oftime to thereby define a peak amplitude; d. integrating said outputsignal during the scanning of the magnetic field to provide a firstintegral signal; e. integrating said first integral signal during thescanning of the magnetic field to provide a second integral signal; f.dividing said second integral signal by said first integral signal toprovide a signal having a value representative of the elapsed timebetweEn the time of occurrence of a centroid of said first ion collectoroutput signal and the termination of the scanning; g. adjusting thelevel of the magnetic field such that ions of a second mass number aredirected substantially toward the ion collector; h. scanning themagnetic field over a range necessary to cause the waveform of a secondoutput signal developed by the ion collector resulting from the ionsstriking the collector to take the form of a signal which increases invalue for a given interval of time and decreases in value for a giveninterval of time to thereby define a peak amplitude; i. integrating saidsecond output signal during the second scanning of the analyzer field toprovide a third integral signal; j. integrating said third integralsignal during the second scanning of the analyzer field to provide afourth integral signal; k. dividing said fourth integral signal by saidthird integral signal to provide another signal having a valuerepresentative of the elapsed time between the time of occurrence of acentroid of said second ion collector output signal and the terminationof the second scanning; and, l. subtracting the value of one of saidelapsed time representative signals from the value of the other elapsedtime representative signal to provide a comparison signal representativeof the relative positions of the signal peaks.
 35. The method as definedin claim 34, including the steps of: a. changing the level of themagnetic field to a different value which also causes the ions of thefirst mass number to be directed substantially toward the ion collector;and b. repeating the steps of c) through f), and h) through l) of claim34.
 36. The method as defined in claim 34 including the steps of: a.changing the level of the magnetic field to a different value which alsocauses the ions of the second mass number to be directed substantiallytoward the ion collector; and, b. repeating the steps of b) through f),and h) through l) of claim 34.